Power usage of system on chip (SOC) integrated circuit (IC) is a major concern during its design. The increasing integration of functions into the SOC with higher and higher speeds of operation has created a need find methods for reducing power consumption. One such method is to selectively switch-off unused portions or functional blocks of the SOC during operation. Such power reduction in SOCs during operation is achieved by performing clock gating, where clock signals (clocks) provided to the Flip-Flops (flops) within the functional block is switched-off thereby disabling the section of the circuit that is not being used.
Typical clock gating can be split into two classes, combinational clock gating and sequential clock gating. Combinational clock gating is the process of computing an explicit enable for a flop and use this enable to gate the clock to the flop. This requires only a combinational analysis of the design, leading to synthesis of a gating circuit for the clock to the flop. Synthesis tools easily perform any required combinational clock gating functionality to reduce the power of an SOC during synthesis.
On the other hand sequential clock gating is the process of computing an implicit enable for a flop. Since this requires a sequential analysis of the design, synthesis tools are not usually equipped to generate and implement such sequential clock gating circuits effectively.
Several specialized techniques to perform sequential clock gating have been published. The most common published techniques are to derive the observability don't care (OCD) condition, that is, the condition for which a flop is not observable; and stability (STC) condition, that is, the condition for which the input value of the flop does not change. It is necessary to identify OCD and STC conditions and use these conditions as an implicit enable to gate the flop.
FIG. 1 is a typical circuit 100 using flip-flops (flops), 111 to 114. These flops are designated FF1 111, FF2 112, FF3 113 and FF4 114. Three of the flops 111 to 113 have respective enable signals EN1 101, EN2 102 and EN3 103. The outputs of the three enabled flops 111, 112 and 113 are multiplexed through a multiplexer 110 to feed FF4 114.
In the above case, existing methods derive an enable, which is a delay of (EN1∥EN2∥EN3). To find this enable, existing methods traverse the fan-in of FF4 114 until reaching the three flops, FF1 111, FF2 112 and FF3 113 and extract the STC condition of these flops; that is the states of enables EN1 101, EN2 102 and EN3 103. It then performs an OR of these enables EN1 101, EN2 102 and EN3 103 and delays them by a clock cycle to compute the final STC condition, that is, the enable of FF4 114.
The resultant circuit 200 diagram is shown in FIG. 2. The enables EN1 101, EN2 102 and EN3 103 of FIG. 2 are fed into a three input OR gate 201. The output of OR gate 201 is delayed by a single clock cycle using the added FF, FF5 202. The output of FF5 202 forms the enable EN4 203, that enables the clock of the flop FF4 114.
However the current methods to compute STC suffer from several limitations. They are not able to identify STC conditions for all cases, they also do not take into account the activity of the net, and finally none of the prior art methods can provide a solution to cover synthesis of clock gating in the case of an existing gated pipeline design. These limitations of the current STC computation are detailed below using the FIG. 3.
FIG. 3 is an exemplary pipeline design 300 where flops F4-1 310, F4-1 311, F4-3 312 and F4-4 313 for a pipeline logic that is enabled by the enable En4 301. The flop F4-1 310 has a synchronous reset connected as a primary input reset. The flop FF3 303 is shown as a flop without an enable associated with it and the flop FF1, 111 is enabled by the enable EN1 101 and the flop FF2 112 is enabled by the enable EN2 102 as shown in FIG. 3 pipeline design 300.
The power dissipation of this pipeline design is a factor of the enable EN4 301 which is used to enable the clock 350 of the pipeline stages. If this enable is set to active, or a value of <1>, for a long period of time, that is, active for a large number of clock cycles at a time, the efficiency of clock gating using EN4 301 is minimum and such clock gating will not decrease the active power of FF4-1 310. Since the clock gating has to be sequentially delayed for the pipeline stages FF4-1 310 to FF4-4 313 the probability of gating based on the pipeline flops is limited and the current methods of deriving STC are not sufficient to compute the STC of the pipeline stage. Further in order to compute the STC of flop FF4-1 310, the fan-in of the first flop FF4-1 310 of the pipeline has to be traversed. The fan-in traversal within the circuit will encounter a primary reset input 304, a flop FF3 303 which is a flop without a reset and two flops FF1 111 and FF2 112 with reset. Though the condition of the flops FF1 111 and FF2 112 have been covered in prior art, the other two conditions, namely having a primary input (PI) and having a flop without enable in the fan-in traversal path, are not covered by the prior art STC computation methods. Due to these limitations the STC of flop FF4-1 cannot be computed using the prior art methods.
It is hence necessary and useful to find a solution that can provide full clock gating synthesis and verification coverage for a gated design including gated pipeline designs.